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Memory architecture
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#	Item
341	Eliminating Cache-Based Timing Attacks with Instruction-Based Scheduling Deian Stefan1 , Pablo Buiras2 , Edward Yang1 , Amit Levy1 , David Terei1 , Alejandro Russo2 , and David Mazières 1 Add to Reading List Source URL: www.amitlevy.com Language: English - Date: 2013-09-13 15:42:52 Cache Computer memory Computer architecture Scheduling Thread Timing attack Computing Central processing unit CPU cache
342	RE SE A RCH F E AT U RE Concurrent Average Memory Access Time Xian-He Sun and Dawei Wang, Add to Reading List Source URL: www.cs.iit.edu Language: English - Date: 2014-05-30 12:12:22 Computer architecture Computer memory Microprocessors Threads CPU cache Cache Memory hierarchy Microarchitecture Parallel computing Computer hardware Computing Central processing unit
343	Conference January 29 - February 1, 2007 Exhibition January, 2007 Santa Clara, California CD-ROM Technical Paper Proceedings Sponsor www.bertscope.com Add to Reading List Source URL: www.designcon.com Language: English - Date: 2014-12-22 13:34:10 Technology Computer memory Rambus Altera Tektronix Field-programmable gate array Signal integrity Advanced Microcontroller Bus Architecture Jitter Electronic engineering Fabless semiconductor companies Electronics
344	A Non-Blocking Reference Listing Algorithm for Mobile Active Object Garbage Collection Wei-Jen Wang and Carlos A. Varela Department of Computer Science, RPI Automatic garbage collection (GC) gives abstraction to distribu Add to Reading List Source URL: wcl.cs.rpi.edu Language: English - Date: 2015-01-22 12:32:43 Inter-process communication Data transmission Distributed computing architecture Message passing Actor model Garbage collection Reference counting Transmission Control Protocol Communications protocol Computing Memory management Concurrent computing
345	DEC Marlboro December 1978 KSREF.MEM for hardware REV 2 ************************************************************************* * Add to Reading List Source URL: bitsavers.trailing-edge.com Language: English - Date: 2000-12-04 13:53:32 Computer architecture PDP-10 Microcode Parity bit Booting Intel Universal asynchronous receiver/transmitter Memory address Computer hardware Computing Data transmission
346	Minimum Requirements for installation of DNA Master PC Minimum Requirements OS: Windows XP/Vista/7 32-bit or 64-bit CPU: Dual-core Processor 1.8GHz Memory: • XP: 1GB Add to Reading List Source URL: phagesdb.org Language: English - Date: 2013-11-06 11:45:24 Microsoft Windows Windows XP Windows Vista Windows Installation Mac OS X Boot Camp Disk partitioning Operating system Software System software Computer architecture
347	AN-2 Application Note 750 Naples Street • Add to Reading List Source URL: www.pumpkininc.com Language: English - Date: 2011-09-12 16:03:12 Computing Microcontrollers Central processing unit Instruction set architectures PIC microcontroller Bank switching Random-access memory Instruction set Computer architecture Computer hardware Computer memory
348	MOTOROLA Radio Service Software (RSSOperational Problem TROUBLESHOOTING FLOWCHART 28aug98Gary Christel Add to Reading List Source URL: www.batlabs.com Language: English - Date: 2011-04-10 17:56:24 DOS memory management Configuration files CONFIG.SYS OS/2 AUTOEXEC.BAT Windows 95 Drive letter assignment DOS Conventional memory Computing Computer architecture Software
349	Episode/Episode Engine Hardware Setup Examples This document provides hardware setup recommendations for the Episode® family ranging from smaller Episode desktop solutions to larger server-based Episode Engine workflows Add to Reading List Source URL: www.telestream.net Language: English - Date: 2014-03-13 13:55:40 Xserve Mac Pro Mac Mini MacBook Pro Xeon MacBook Multi-channel memory architecture Nehalem Dell Inspiron Computing Apple Inc. Personal computers
350	Optimizing Software Data Prefetches with Rotating Registers Gautam Doshi Intel Corporation 2200, Mission College Blvd Santa Clara, CA 95052 Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:06 Computer hardware Computer memory Software pipelining AMD 10h Loop unwinding CPU cache Branch predication Explicitly parallel instruction computing Compiler optimizations Computing Computer architecture

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